The University of Alabama (UA) IRES program Design and Characterization of Fractional-Order Microelectronic Circuits and Devices in Czechia, is a collaborative research experience between the Department of Electrical and Computer Engineering at UA and the the UA and the Faculty of Electrical Engineering and Communication at the Brno University of Technology (BUT) in Czechia (Czech Republic). This program spans up to 12 weeks during the summer semester to immerse 6 students from UA in research on fractional-order circuits and systems at BUT (under the mentorship of Dr. Freeborn and faculty in Brno). Students from electrical engineering and computer engineering are encouraged to apply.
The goal is to help prepare a new generation of engineers who are ready to meet the growing demands of the U.S. semiconductor and microelectronics industry. Through hands-on experience in designing and building circuits, students will gain valuable technical skills while also learning to work as a member of an international team. By living and working in Brno for 12-weeks during the summer, students will gain a deeper understanding of different cultures and global collaboration in engineering. Students will investigate challenges such as modeling and fabricating fractional-order components, designing new types of circuits for signal processing using fractional-order components, and using fractional-order electrical models to analyze crops and liquids for food safety. These projects require both theoretical understanding and practical skills in electronics design, simulation, fabrication, and validation. With support from expert mentors at BUT, students contribute to advancing fractional-order systems while gaining skills directly aligned with future U.S. workforce needs in microelectronics.
Previous Research
To help illustrate the types of projects in this program, examples of the research that previous students completed (and then presented/published), include:
- C. Duckworth, R. Sotner, J. Jerabek, T.J. Freeborn, “Fractional-order equivalent circuit representation of sucrose solutions electrical impedance measured in bipolar configuration,” IEEE SoutheastCon, Concord, U.S.A., pp. 1487-1493 2025.
- L.A. Prokup, D. Kubanek, T.J. Freeborn, “Finite element model in LTspice of a distributed RC-structure fractional-order capacitor device,” IEEE SoutheastCon, Concord, U.S.A., pp. 1494-1500, 2025.
- R. Aldridge, D. Kubanek, J. Koton, T.J. Freeborn, “Generalized approach for fractional-order low-pass Butterworth filter realization with a inverse follow the leader filter (iflf) topology,” IEEE SoutheastCon, Concord, U.S.A., pp. 1596-1602, 2025.
- M. McGowan, D. Kubanek, N. Herencsar, T.J. Freeborn, “Transitional frequencies of fractional-order transitional transfer functions using Butterworth and Sync-Tuned approximations,” IEEE SoutheastCon, Concord, U.S.A., pp. 1609-1614, 2025.
- C. Black, J. Jerabek, R. Sotner, T.J. Freeborn, “Emulation of fractional-order impedance with α = 0.5 using MOSFET revised RC-ladder topology,” IEEE Southeast Con., pp. 1223-1228, Atlanta, U.S.A., 2024.
- K. Cantrell, J. Jerabek, J. Koton, T.J. Freeborn, “Fractional-order immitance converter (FGIC44) performance using wideband fractional-order element seeds,” IEEE Southeast Con., pp. 1216-1222, Atlanta, U.S.A., 2024.
- R. Kerr, J. Jerabek, R. Sotner, T.J. Freeborn, “Exploring the effect of electrode material on the electrical impedance of liquid samples,” IEEE Southeast Con., pp. 1099-1105, Atlanta, U.S.A., 2024.
- O. Van Fleet, L. Conway, N. Herencsar, T.J. Freeborn, “Fractional-order equivalent circuit representation of Kohlrabi tissue samples,” IEEE Southeast Con., pp. 1034-1039, Atlanta, U.S.A., 2024.
Important Dates:
- Final Application Deadline: November 30, 2025 (@11:59PM)
- Notification Deadline: December 14, 2025
- Expected Program Dates: May 4, 2026 to July 24, 2026.
Contact
For more information about this program, contact the program coordinator:
Application
Complete the online application (on the NSF ETAP portal) by the deadline for full consideration. We reserve the right to make offers to promising applicants before the deadline. The application will require you to upload your CV/resume, transcripts (unofficial copy is acceptable), and complete program specific questions that will help with the selection process.
Benefits
- Contribute to research projects focused on circuits and systems during collaboration with faculty at UA (Dr. Freeborn) and faculty mentors at BUT.
- Attend professional development seminars to supplement research training (covering topics including literature searches, academic authorship, semiconductor careers, graduate school, and scientific presentations)
- Explore Czechia and cultural/regional attractions
- Present research results at end of summer virtual symposium to project team
Financial Support
Participant will receive:
- Stipend ($8400 for the summer)
- Travel expenses to/from Brno, Czechia fully covered by program
- Accommodation in student residence at BUT (expenses covered by program)
- Travel / emergency medical insurance (expenses covered by program)
Change Requirements
Participant must:
- Complete electric circuits related coursework (Required: ECE 225, ECE 332 or equivalent, Preferred: ECE 225, ECE 332, ECE 333) prior to travel
- Complete 2-credit hour prep course (ECE 399) with Dr. Freeborn during the Spring 2026 semester
- Commit at least 40 hours per week to research and cultural activities during the summer program
- Attend professional development workshops and research seminars during the summer
- Attend social events (Trips to Prague and other cultural sites in Czechia) during the summer